Design and performances of a compensated mean timer


R. Foglio, J. Pouxe, O. Rossetto.


ISN 99-07 Janvier 1999



Abstract

An integrated mean timer has been designed. This circuit integrates a compensation system in order to minimize thermal drift and process variations. This circuit designed in BiCMOS 0.8mm integrates input and output ECL translators. The drift cancelation system is based on a regulated delay line controlled by a PLL. The PLL circuit can be disconnected and an external voltage control can be used. The circuit can also run without any cancelation system.



I. Introduction

In physic experiments, the pulse delay comming from a large detector (scintillators) depends on the position of the incident particles in the scintillator. In order to obtain an information on the time of the incident particle, a photomultiplier tube is used at each extremity of the scintillator. The average time between the two pulses allows to determine the time of the particle arrival. In order to estimate this average time, an integrated mean timer circuit has been designed. In order to have a compact system, two mean timers are integrated on the same chip.



II. Mean timer principle

One solution to realize the mean timer function, is to implement two delay lines, with opposite propagation direction, each input of a delay line is the input of the mean timer. It is possible to extract the average time simply by realizing the coincidence between the two pulses that are propaging into the delay lines. The figure 1 describes this principle. In order to be able to realize the coincidence between the two propaging pulses, the delay line have to be discretized. The most simple solution to integrate such a delay line is to use the intrinsic delay of an inverter and to cascade a certain number of inverters in order to obtain the required total delay (see fig 2).

Figure 1 : mean timer principle Figure 2 : delay line implementation

The main drawback of such delay line is that the delay is process and temperature dependent. Simulation results on a simple inverter show that the thermal drift is about 15%/50° on the inverter delay. Another important result is the process variation. Simulation shows that from the worst case to the best case, the delay on an inverter can vary more than 100%. Such variations are incompatible with the accuracy requirement for the mean timer. For these reasons, an internal compensation system has been designed.

The theoretical resolution of such system is limited by the quantization step of the delay line. Sub-micron technology have reached intrinsic delays of an inverter which are compatible with the requirement (typical delay 100 to 300 ps).

The theoretical jitter of this circuit will be given by the mismatching delay path on the coincidence logic. With a skill sizing of the transistors composing this glue logic, a jitter lower than 100 ps can be expected.



III. PLL delay regulation

In order to control the delay of an inverter, its structure has been modified into a cell called starved inverter. In this cell, the inverter is powered through two transistors : one NMOS connected to ground that can control the falling edge delay, and one PMOS connected to Vdd that can control the rising edge delay. The schematic of such a delay cell is given on figure 3. As we want to keep the inverter characteristic as symetric as possible (same Tphl ans Tplh), two "degenerating transistors are used (one PMOS on the Vdd power supply to control the Tplh, and one NMOS to the ground path in order to control the Tphl delay). The two corresponding control voltages (Vcn and Vcp) have to be controlled in opposite variation. This is achieved by a simple amplifier with a -1 gain, designed simply with 2 transistors as shown on figure 4.

By this way, we can build a voltage controlled delay line. The remaining problem is then how generating this control voltage in order to cancel thermal and process variations.

Figure 3 : the starved inverter schematic Figure 4 : -1 gain amplifier

One solution is the use of a PLL system. The PLL is composed of a local (integrated) Voltage Controlled Oscillator. The phase of this VCO is compared with a reference clock. The phase error between the two clocks is fed back on the control voltage input of the VCO. Such a system ensure that the internal oscillator has exactly the reference oscillator frequency (see figure 5).
Figure 5 : the PLL principle

If the VCO is composed of the same starved inverter that those used in the delay line, the variations of the characteristics of the delay line can be controlled. It is simple to realize an oscillator using a ring oscillator composed of an odd number of inverters. The thermal drift observed with such a system will be the thermal drift of the reference clock. If this external reference is implemented with a crystal oscillator, the thermal drift can be reduced to a few ppm/°C. The figure 6 gives the principle of the PLL compensated mean timer.
Figure 6 : the compensated mean timer principle

On the figure 6, we added a resistor between the output of the PLL and the voltage control input of the delay line. This resistor doesn't modify the principle as the voltage control input of the delay line is at high impedance (gate of MOS transistors). This resistor allows us to add an external control that can be used to force with a external voltage the charateristic of the delay lines. On this schematic, we can remark that the delay line is loaded by the coincidence gate. In order to have exactly the same delay for the cells used in the ring oscillator and in the delay lines, we loaded the ring oscilator with a dummy coincidence gate (not represented on this schematic).



IV. The coincidence gate

The mean timer, as it has been presented has theoreticaly no jitter. In fact, the coincidence gate is a complex one with 80 inputs as the delay lines are composed of 80 cells. If for the coincidence gate, the delay from one input to an other is different, this will be create a delay error at the output interpreted as jitter. The gate level schematic of the meantimer core (including the delay lines and the coincidence gate) is given in annex A.



V. Glue logic

All the structure presented is implemented in CMOS structure. Le logical value in such a case are Vdd for a 1 and Gnd for a 0. As the mean timer is designed to be used in a high speed system, all critical signals are ECL. The circuit integrates input ECL to TTL translators and output TTL to ECL translators. Only the external clock reference has to be in TTL levels. The output pulse duration is equal to the input pulses ones. In order to have a larger pulse, a second output has been added. This second output has se same function than the first one but the signal comes from a monostable. The pulse duration of the monostable output can be adjusted by adding an external resistor.



VI. Layout considerations

The coincidence gate could be completely implemented with standard cells (NAND and NOR). For mainly two reasons, we redesigned the cells and didn't used an automatic place and route for this block : The first reason is that in a standard cell, the delays are not exactly the same for all the inputs because in a simple cell (for example a NAND) all NMOS transistors have the same size for area optimization. Due to the body effect, one NMOS is slower than the other. To compensate this effect, we redesigned our own cells with a special sizing for all the transistors. The second reason, is that it is impossible to control exactly the mismatching delay with an automatic place and route tool. In this design, all the wires used into de coincidence gate are implemented with the same metal level in order to have the same parasitic capacitance, and have exactly the same length. The VCO and the delay lines are also full custom as the starved inverter is not a standard cell and also for accuracy reason like in the coincidence gate.
The circuit has been designed with the AMS 0.8mm BiCMOS technology. Bipolar transistors are used only in the translators. The complete layout of this circuit is shown on figure 7. The total area of the circuit is 2.4x2.6 mm2. The circuit has been packaged into a PLCC28 pin package. The pinout of the circuit is given on figure 8 (the detail of each pin function is given in annex B).

Figure 7 : Layout of the mean timer Figure 8 : pinout of the circuit



VI. Test results

The characteristics of the circuit have been measured with three configuration : without any compensation, with the PLL compensation and with an external compensation.

Without Comp. PLL Comp.external Comp.
Resolution (ps)125125 125
Jitter (ps rms - WHM)<50 <150 (1)<50
Drift (ps/°C)>30 <12 (2)<6
Power dissipation(mW)<100 <100 (3)<100
Power supply (V)+/- 2.5 +/- 2.5+/- 2.5

Notes :

(1) : The jitter is worth with the PLL compesation due to the digital noise received by the control voltage. This control voltage exhibits a 50mV noise that make some variations on the delay. These variations are observed at the output as a jitter. The lower the amplitude of the external clock is, the lower the jitter is. The jitter is depending on the external clock frequency (best results with a clock frequency around 20MHz that means a longer delay line).

(2) : The PLL compensation compensates only the delay line drift. The coincidence gates and translators are not conpensated. The resulting drift is caused by the uncompensated gates. The delay line is completely compensated. The external compensation gives better results because it is a global compensation : the delay lines and all the other gates are compensated. The principle of the external compensation is given on figure 9.

(3) : with the PLL compensation active (20MHz clock frequency), the power comsumption is 2mW bigger due to the clock buffers and phase comparator.


Figure 9 : the external compensation system

The LM335 is the temperature sensor, that deliver 10mV/°C, the resistor ADJ1 is used to ajust the offset that compensate the process variation.


VII. Conclusion

The mean timer characteristics are compatible with most requirement in physic experiments. The results show that it is necessary to design a thermal compensation system. The integrated compensation system with the PLL provides a good thermal and process variation compensation. The main problem with this PLL is the digital noise that gives a large jitter at the output. The external solution gives better result for the thermal compensation, and for the jitter. But this method doesn't compensate automaticaly the process variation and a manual trimming may be done. On this circuit, the resolution of the mean timer is limited by the unit delay of the starved inverter. Many solution can be imagined to improve this resolution :



Annex A : simplified schematic of the meantimer core

Annex B : pins function :

Clk : PLL clock input (-2.5 ; 2.5 volts level)

Cntr : voltage control input

I1b+ : non inverting input n°1 meantimer n°2 (ECL level).

I1b- : inverting input n°1 meantimer n°2 (ECL level).

I2b+ : non inverting input n°2 meantimer n°2 (ECL level).

I2b- : inverting input n°2 meantimer n°2 (ECL level).

Enb : Enable meantimer n°2 (ECL level).

Ob+ : non inverting output meantimer n°2 (ECL level).

Ob+ : inverting output meantimer n°2 (ECL level).

Omb+ : monostable non inverting output meantimer n°2 (ECL level).

Omb- : monostable inverting output meantimer n°2 (ECL level).

Wb : width monostable output adjust meantimer n°2.

I1b+ : non inverting input n°1 meantimer n°2 (ECL level).

I1b- : inverting input n°1 meantimer n°2 (ECL level).

I2b+ : non inverting input n°2 meantimer n°2 (ECL level).

I2b- : inverting input n°2 meantimer n°2 (ECL level).

Enb : Enable meantimer n°2 (ECL level).

Ob+ : non inverting output meantimer n°2 (ECL level).

Ob- : inverting output meantimer n°2 (ECL level).

Omb+ : monostable non inverting output meantimer n°2 (ECL level).

Omb- : monostable inverting output meantimer n°2 (ECL level).

Wb : width monostable output adjust meantimer n°2.

V- : -2.5 volts power supply

V+ : +2.5 volts power supply

GND : Ground